High Performance THANVaS Memories for MLC Charge Trap NAND Flash

Author

Suhane, A. ; Van den Bosch, G. ; Arreghini, A. ; Breuil, L. ; Cacciato, A. ; Zahid, M.B. ; Debusschere, I. ; De Meyer, K. ; Van Houdt, J.

Author_Institution

imec, Leuven, Belgium

fYear

2011

fDate

22-25 May 2011

Firstpage

1

Lastpage

4

Abstract

In this paper we investigate THANOS and THANVaS memory devices featuring a 2 nm HfO₂ capping layer on top of the AI₂O₃ blocking dielectric. Furthermore, we benchmark these devices against reference TANOS and TANOS with variable tunnel oxide thickness (TANVaS), respectively. It is found that HfO₂ capping layer improves erase saturation level due to its better electron blocking capabilities during erase operation, as also confirmed by simulations. As a result of improved erase saturation, THANVaS device shows excellent performance of 9.5 V memory window with flat endurance up to 10⁴ cycles and improved high temperature retention.

Keywords

NAND circuits; alumina; aluminium compounds; flash memories; hafnium compounds; silicon compounds; tantalum compounds; Al₂O₃; HfO₂; MLC charge trap NAND flash; TANOS with variable tunnel oxide thickness; THANOS memory devices; THANVaS memory devices; TaN-AlO-SiN-SiO-Si; capping layer; electron blocking capabilities; erase saturation level; high temperature retention; size 2 nm; voltage 9.5 V; Aluminum oxide; Charge carrier processes; Logic gates; Performance evaluation; Programming; Transient analysis;

fLanguage

English

Publisher

ieee

Conference_Titel

Memory Workshop (IMW), 2011 3rd IEEE International

Conference_Location

Monterey, CA

Print_ISBN

978-1-4577-0225-9

Electronic_ISBN

978-1-4577-0224-2

Type

conf

DOI

10.1109/IMW.2011.5873210

Filename

5873210