DocumentCode :
3518262
Title :
A Novel FN Erasable Undercut Device Containing Two Physically Separated Nitride Storage Nodes Per Cell Suitable for Advanced NOR Flash Memory Technology
Author :
Chung, S.-Y. ; Chan, S. ; Chang, K.-T. ; Davis, B. ; Kathawala, G. ; Ko, K. ; Lee, S.-C. ; Liu, Z. ; Lin, C. ; Ohtsuka, K. ; Park, S.-H. ; Thurgate, T. ; Xue, L. ; Randolph, M. ; Shiraiwa, H. ; Sun, Y. ; Chang, C.
Author_Institution :
Spansion, Inc., Sunnyvale, CA, USA
fYear :
2011
fDate :
22-25 May 2011
Firstpage :
1
Lastpage :
2
Abstract :
A novel NOR Flash cell with a build-in 2-bit capability consisting of two physically isolated ONO charge-storage nodes separated by an oxide dielectric in between over the channel region is demonstrated. This memory cell employs the virtual ground array architecture, much like NROM arrays, is sensed with the reverse read scheme. However, comparing to NROM, this novel cell offers a wider Vt window due to the reduction of the ´second bit´ effect which is a concern in NROM cell scaling. The two separated storage nodes are fabricated by a self-aligned ´undercut´ process. The undercut cell is programmed by channel hot electron and erased by Fowler-Nordheim (FN) electron tunneling thus removing any concern with hole-injection induced degradation. The FN erase is made possible by the introduction of a band-gap engineered nitride material as the charge storage medium. Another important merit is its immunity to cell over erasure owing to the presence of the ´enhancement-mode´ oxide channel region.
Keywords :
NOR circuits; flash memories; hot carriers; nitrogen; tunnelling; FN erasable undercut device; Fowler-Nordheim electron tunneling; N2; NOR flash memory technology; band-gap engineered nitride material; channel hot electron; enhancement-mode oxide channel region; hole-injection induced degradation; isolated ONO charge-storage nodes; nitride storage nodes; oxide dielectric; reverse read scheme; second bit effect reduction; self-aligned undercut process; virtual ground array architecture; word length 2 bit; Arrays; Channel hot electron injection; Degradation; Fabrication; Logic gates; Microprocessors;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Memory Workshop (IMW), 2011 3rd IEEE International
Conference_Location :
Monterey, CA
Print_ISBN :
978-1-4577-0225-9
Electronic_ISBN :
978-1-4577-0224-2
Type :
conf
DOI :
10.1109/IMW.2011.5873212
Filename :
5873212
Link To Document :
بازگشت