DocumentCode
3518324
Title
A True 6F2 NOR Flash Memory Cell Technology - Impact of Floating Gate B4-Flash on NOR Scaling
Author
Shimizu, S. ; Shukuri, S. ; Ajika, N. ; Ogura, T. ; Mihara, M. ; Kawajiri, Y. ; Kobayashi, K. ; Nakashima, M.
Author_Institution
GENUSION, Inc., Amagasaki, Japan
fYear
2011
fDate
22-25 May 2011
Firstpage
1
Lastpage
2
Abstract
This paper describes a true 6F2 B4-Flash (Back Bias assisted Band-to-Band tunneling induced Hot Electron injection Flash) memory cell, which is one half of conventional NOR cell, for the first time as a floating gate NOR cell. 6F2 B4-Flash cells featuring a self-aligned STI and self aligned contact architectures have been fabricated by a 90nm process and was confirmed sufficient performance for NOR array operation. The cell size of 0.0486um2 of 90nm 6F2 is the smallest NOR cell in the 90nm generation. B4-HE programming scheme, in which the voltage between drain and source sets to 1.8V, allows more aggressive gate length scaling than for conventional CHE programming cells, consequently gate length has been scaled down to 78nm.
Keywords
NOR circuits; cellular arrays; flash memories; hot carriers; tunnelling; 6F2 NOR flash memory cell technology; B4-HE programming scheme; CHE programming cell; NOR array operation; aggressive gate length scaling; back bias assisted band-to-band tunneling; floating gate B4-flash; hot electron injection flash memory cell; self-aligned STI; self-aligned contact architecture; size 78 nm; size 90 nm; voltage 1.8 V; Arrays; Junctions; Logic gates; Microprocessors; Nonvolatile memory; Programming;
fLanguage
English
Publisher
ieee
Conference_Titel
Memory Workshop (IMW), 2011 3rd IEEE International
Conference_Location
Monterey, CA
Print_ISBN
978-1-4577-0225-9
Electronic_ISBN
978-1-4577-0224-2
Type
conf
DOI
10.1109/IMW.2011.5873217
Filename
5873217
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