Title :
A novel 0.7 V two-port 6T SRAM memory cell structure with single-bit-line simultaneous read-and-write access (SBLSRWA) capability using partially-depleted SOI CMOS dynamic-threshold technique
Author :
Liu, S.C. ; Kuo, J.B.
Author_Institution :
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
Abstract :
Summary form only given. This paper reports a novel low-voltage two-port 6T SRAM memory cell structure with single-bit-line simultaneous read-and-write access capability using a partially-depleted SOI CMOS dynamic-threshold technique. With an innovative approach connecting the body terminal of an NMOS device in the latch and the write access pass transistor to the write word line, this 6T memory cell can be used to provide SBLSRWA capability for 0.7 V two-port SOI CMOS VLSI SRAM, as verified by MEDICI results.
Keywords :
CMOS memory circuits; SRAM chips; VLSI; circuit simulation; low-power electronics; silicon-on-insulator; 0.7 V; MEDICI simulation; NMOS device; SBLSRWA capability; Si-SiO/sub 2/; body terminal; latch; low-voltage two-port SRAM memory cell structure; partially-depleted SOI CMOS dynamic-threshold technique; single-bit-line simultaneous read-and-write access; single-bit-line simultaneous read-and-write access capability; two-port SOI CMOS VLSI SRAM; two-port SRAM memory cell structure; write access pass transistor; write word line; CMOS logic circuits; CMOS memory circuits; CMOS technology; Joining processes; Latches; Logic devices; MOS devices; Random access memory; Read-write memory; Threshold voltage;
Conference_Titel :
SOI Conference, 1999. Proceedings. 1999 IEEE International
Conference_Location :
Rohnert Park, CA, USA
Print_ISBN :
0-7803-5456-7
DOI :
10.1109/SOI.1999.819860
