Investigation of wire bonding power interconnection

Author

Novotny, Marek ; Bursik, Martin ; Szendiuch, Ivan ; Hejatkova, Edita ; Jankovsky, Jaroslav

Author_Institution

Dept. of Microelectron., Brno Univ. of Technol., Brno, Czech Republic

fYear

2010

fDate

12-16 May 2010

Firstpage

166

Lastpage

169

Abstract

This paper deals with the investigation of wire bonding power interconnection for standard CMOS chips, which is very important for power application. Base part of this research is the determination of power load by the wire. For testing are design two types of substrate, especially the FR4 and ceramic substrate. As a conductive thick film layer on the ceramic substrate is used two different pastes. First paste was AgPd and the second one AgPdPt. Various wire interconnections are made on each substrate. This contact are analyzing in term of power load. The evaluation of test is based on the value of power load, wire diameter, type of conductive layer on the substrate, etc.

Keywords

CMOS integrated circuits; integrated circuit interconnections; lead bonding; palladium compounds; silver compounds; AgPdPt; FR4 substrate; bonding power interconnection; ceramic substrate; conductive thick film layer; power application; power load; standard CMOS chips; wire diameter; Bonding; Contacts; Heating; Integrated circuit interconnections; Joints; Substrates; Wire;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics Technology (ISSE), 2010 33rd International Spring Seminar on

Conference_Location

Warsaw

Print_ISBN

978-1-4244-7849-1

Electronic_ISBN

978-1-4244-7850-7

Type

conf

DOI

10.1109/ISSE.2010.5547282

Filename

5547282