DocumentCode
3518376
Title
A dynamic body discharge technique for SOI circuit applications
Author
Kuang, J.B. ; Saccamango, M.J. ; Lu, P.F. ; Chuang, C.T. ; Assaderaghi, F.
Author_Institution
IBM Corp., Rochester, MN, USA
fYear
1999
fDate
4-7 Oct. 1999
Firstpage
77
Lastpage
78
Abstract
It has been reported (Kuang et al., 1997; Lu et al., 1997) that SOI passgate circuits suffer history effects and adverse initial-cycle parasitic bipolar currents, which cause difficulties in circuit timing and limit direct design reuse from original bulk circuits. SOI device body history can also induce transfer characteristics mismatch in dual-railed static or dynamic CMOS circuits, resulting in speed degradation or functional failures. This paper describes an efficient technique to alleviate initial-cycle bipolar currents while retaining the low-V/sub t/ floating body feature when the SOI devices concerned are on. We also present a dynamic body discharge technique to eliminate the mismatch problems in cross-coupled SOI CMOS topologies, for use in a variety of circuit families such as cascade voltage switch logic, latch-type sense amplifiers and analog operational amplifiers.
Keywords
CMOS analogue integrated circuits; CMOS logic circuits; cascade networks; integrated circuit design; network topology; operational amplifiers; silicon-on-insulator; timing; SOI circuit applications; SOI device body history; SOI devices; SOI passgate circuits; Si-SiO/sub 2/; analog operational amplifiers; bulk circuits; cascade voltage switch logic; circuit timing; cross-coupled SOI CMOS topologies; direct design reuse; dual-railed dynamic CMOS circuits; dual-railed static CMOS circuits; dynamic body discharge technique; functional failures; history effects; initial-cycle bipolar currents; initial-cycle parasitic bipolar currents; latch-type sense amplifiers; low-threshold voltage floating body feature; speed degradation; transfer characteristics mismatch; CMOS analog integrated circuits; CMOS logic circuits; Circuit topology; Degradation; History; Operational amplifiers; Switches; Switching circuits; Timing; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
SOI Conference, 1999. Proceedings. 1999 IEEE International
Conference_Location
Rohnert Park, CA, USA
ISSN
1078-621X
Print_ISBN
0-7803-5456-7
Type
conf
DOI
10.1109/SOI.1999.819861
Filename
819861
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