Scalability of fully-depleted SOI technology into 0.13 /spl mu/m 1.2 V-1 V CMOS generation

Scalability of SOI technology into 0.13 /spl mu/m 1.2 V CMOS has been demonstrated for partially-depleted (PD) devices (Leobandung et al., 1998). Propagation delay versus active power can be greatly reduced by using fully-depleted (FD) devices, because threshold voltage (V/sub t/) and junction capacitance (increased by halo implant in case of bulk and PD devices) are lower. However, this advantage is possible only if transconductance is not degraded by high S/D resistance and if SCE and DIBL are well controlled, essentially by reducing silicon thickness. Furthermore, sensitivity of electrical parameters to silicon thickness (tsi) for FD devices is often mentioned as a critical process issue due to SOI substrate thickness nonuniformity. In this paper, we show (with both 2D simulations and measurements) that V/sub t/ control can be improved by a low energy S/D implant for enhancement-mode (EM) devices. S/D resistance can also be maintained at a low enough level by using a recessed-channel process, which allows the proper reduction of tsi exactly under the gate (Raynaud et al., 1998). Using a TiSi/sub 2/ salicide process on gate and elevated S/D regions, we have measured a maximum oscillation frequency f/sub max/ of 48 GHz at 0.9 V for 0.25 /spl mu/m NMOS. Finally, we show that, due to a balance between different physical effects, the distribution of critical parameters for digital applications (saturation and off currents, propagation delay and power consumption) is not degraded by silicon thickness nonuniformity.