Alternative source/drain contact-pad architectures for contact resistance improvement in decanano-scaled CMOS devices

A method for decreasing the parasitic source and drain contact resistances in decanano-scaled CMOS devices is presented in this work. The improvement of the electrical performance of the CMOS devices has been achieved by increasing the active contact area, without increasing the complete layout area consumption of the device, for lowering the parasitic source/drain contact resistances. Numerical simulations have been performed for investigating the influences of the new contact pad architectures on the electrical device behavior.