A Novel Reconfigurable Sensing Scheme for Variable Level Storage in Phase Change Memory

Author

Li, Jing ; Wu, Chao-I ; Lewis, Scott C. ; Morrish, Jackie ; Wang, Tien-Yen ; Jordan, Richard ; Maffitt, Tom ; Breitwisch, Matthew ; Schrott, Alejandro ; Cheek, Roger ; Lung, Hsiang-Lan ; Lam, Chung

Author_Institution

IBM T. J. Watson Res. Center, Yorktown Heights, NY, USA

fYear

2011

fDate

22-25 May 2011

Firstpage

1

Lastpage

4

Abstract

This paper presents a novel reconfigurable sensing scheme with the flexibility to change reading precision of analog resistance levels for MLC PCM. A 2Mcell PCM chip was fabricated in 90nm CMOS technology and was tested. Operating at 8-bits precision (adequate for 7b/cell PCM i.e., 128 resistance levels), read access latency is 5μs (measured at 50MHz clock), compared to 35-50μs in state-of-art 2b/cell NAND Flash.

Keywords

CMOS digital integrated circuits; NAND circuits; flash memories; phase change memories; 2Mcell PCM chip; CMOS technology; NAND flash; analog resistance levels; frequency 50 MHz; phase change memory; reconfigurable sensing scheme; size 90 nm; time 35 mus to 50 mus; time 5 mus; variable level storage; word length 8 bit; Clocks; Electrical resistance measurement; Flash memory; Phase change materials; Radiation detectors; Resistance;

fLanguage

English

Publisher

ieee

Conference_Titel

Memory Workshop (IMW), 2011 3rd IEEE International

Conference_Location

Monterey, CA

Print_ISBN

978-1-4577-0225-9

Electronic_ISBN

978-1-4577-0224-2

Type

conf

DOI

10.1109/IMW.2011.5873227

Filename

5873227