• DocumentCode
    3518635
  • Title

    SOI formation from amorphous silicon by metal-induced-lateral-crystallization (MILC) and subsequent high temperature annealing

  • Author

    Jagar, S. ; Mansun Chan ; Poon, K.C. ; Hongmei Wang ; Ming Qin ; Shivani, S. ; Ko, P.K. ; Yangyuan Wang

  • Author_Institution
    Dept. of Electr. & Electron. Eng., Hong Kong Univ. of Sci. & Technol., Hong Kong
  • fYear
    1999
  • fDate
    4-7 Oct. 1999
  • Firstpage
    112
  • Lastpage
    113
  • Abstract
    In current SOI technology, the formation of circuit elements requires the use of some special starting material like SIMOX, BESOI or Unibond wafers, which usually cannot be made in-house. As such, it leads to a divergence between SOI technology and bulk technology, and there are debates on justification on the initial material cost. TFTs formed in polysilicon have similar structures to SOI, and have been used as the load element in SRAM. Comparing TFT and SOI transistors, the TFT is easier to fabricate in term of starting material and compatibility with bulk processes. However, its performance is usually very poor for high performance circuits. The TFT structure consists of a large number of small size crystallized silicon grains. It is desirable to have a very large grain size so that a single transistor can lie entirely on a single grain. In this case, the TFT becomes an SOI MOSFET. Metal-induced-lateral-crystallization (MILC) has been used to enlarge the polysilicon TFT grain size. However, due to the limitation in low temperature formation, the grain size is still not desirable. With the use of high temperature annealing at a temperature above 900/spl deg/C after MILC, we found that much larger crystals of the order of 10 /spl mu/m can be formed. For the advanced technology which comes with device scaling, it is possible to individually recrystallize the active region of each transistor, giving TFTs (as formed) with SOI MOSFET performance.
  • Keywords
    MOSFET; annealing; crystallisation; grain size; integrated circuit technology; recrystallisation; semiconductor technology; silicon-on-insulator; thin film transistors; BESOI wafers; MILC; SIMOX wafers; SOI MOSFET; SOI MOSFET performance; SOI formation; SOI technology; SOI transistors; SRAM load element; Si; Si-SiO/sub 2/; TFT structure; TFTs; Unibond wafers; amorphous silicon; annealing temperature; bulk process compatibility; circuit element formation; crystal size; crystallized silicon grains; device scaling; grain size; high performance circuits; high temperature annealing; initial material cost; low temperature formation; metal-induced-lateral-crystallization; polysilicon TFT grain size; polysilicon TFTs; recrystallization; Amorphous silicon; Annealing; Costs; Crystalline materials; Crystallization; Grain size; MOSFET circuits; Random access memory; Temperature; Thin film transistors;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    SOI Conference, 1999. Proceedings. 1999 IEEE International
  • Conference_Location
    Rohnert Park, CA, USA
  • ISSN
    1078-621X
  • Print_ISBN
    0-7803-5456-7
  • Type

    conf

  • DOI
    10.1109/SOI.1999.819878
  • Filename
    819878