DocumentCode
3518665
Title
0.5V Bit-Line-Voltage Self-Boost-Programming in Ferroelectric-NAND Flash Memory
Author
Zhang, Xizhen ; Miyaji, Kousuke ; Takahashi, Mitsue ; Takeuchi, Ken ; Sakai, Shigeki
Author_Institution
Nat. Inst. of Adv. Ind. Sci. & Technol., Tsukuba, Japan
fYear
2011
fDate
22-25 May 2011
Firstpage
1
Lastpage
4
Abstract
Self-boost-programming for ferroelectric-NAND (Fe-NAND) flash memory was investigated by using a miniature memory cell array, which could reduce bit-line voltages for programming. As the best performance, 0.5V bit-line-voltage programming with 10μs-pulse width was successfully demonstrated. This study indicated that the Fe-NAND flash memory can be operated by much lower power consumption than that of a conventional floating gate (FG-) NAND.
Keywords
NAND circuits; ferroelectric storage; flash memories; bit-line-voltage self-boost-programming; ferroelectric-NAND Flash Memory; miniature memory cell array; power consumption; voltage 0.5 V; Arrays; Flash memory; Logic gates; Nonvolatile memory; Programming; Silicon; Transistors;
fLanguage
English
Publisher
ieee
Conference_Titel
Memory Workshop (IMW), 2011 3rd IEEE International
Conference_Location
Monterey, CA
Print_ISBN
978-1-4577-0225-9
Electronic_ISBN
978-1-4577-0224-2
Type
conf
DOI
10.1109/IMW.2011.5873233
Filename
5873233
Link To Document