A VLSI implementation of a CMOS clock recovery circuit based on edge detection

This paper describes the implementation of a CMOS clock recovery circuit (CRC) based on the PLL architecture, which has an edge detector stage at the input. The system provides frequency detection of random inputs and is therefore well suited to clock recovery in data communications. The NRZ input data signal is differentiated and full-wave rectified in the same circuit in order to show the second order harmonic clearly. Next, the PLL locks to this input signal and provides the clock recovered to its output. The proposed circuit operates at 700Mb/s and exhibits a relatively wide capture range (90MHz) so that the circuit can lock to the input in the presence of temperature, supply voltage and process variations. The CRC circuits exhibit a current consumption of 29mA from a 3.3V supply voltage. The simulations performed in a 0.18μm CMOS technology confirm the theoretical results.