Title :
Fractional implantation area effects on patterned ion-cut silicon layer transfer
Author :
Yun, C.H. ; Cheung, N.W.
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
Abstract :
By masking the gate dielectric area of MOS devices during hydrogen implantation, patterned ion-cut can transfer processed IC device layers to other substrates (Lee et al. 1996; Roberds et al. 1998; Yun et al. 1998). Previous results showed that a 16 /spl mu/m/spl times/16 /spl mu/m nonimplanted region can be cleaved with a 4 /spl mu/m implanted area surrounding it. However, surface morphology of the cleaved Si(100) samples was rough, with a total thickness variation (TTV) of /spl sim/0.4 /spl mu/m for a 1.3 /spl mu/m-thick silicon layer transfer. In order to improve the roughness, we have investigated the fractional implantation area (FIA) effects on the transferred layer surface morphology.
Keywords :
MOS integrated circuits; dielectric thin films; doping profiles; ion implantation; masks; silicon-on-insulator; surface topography; wafer bonding; 1.3 micron; 16 micron; MOS devices; Si-SiO/sub 2/; cleaved Si(100) samples; fractional implantation area effects; gate dielectric area masking; hydrogen implantation; implanted area; nonimplanted region; patterned ion-cut layer transfer; patterned ion-cut silicon layer transfer; processed IC device layer transfer; silicon layer transfer; surface morphology; surface roughness; total thickness variation; transferred layer surface morphology; Annealing; Dielectric substrates; Hydrogen; Plasma temperature; Rough surfaces; Shape; Silicon; Surface morphology; Surface roughness; Wafer bonding;
Conference_Titel :
SOI Conference, 1999. Proceedings. 1999 IEEE International
Conference_Location :
Rohnert Park, CA, USA
Print_ISBN :
0-7803-5456-7
DOI :
10.1109/SOI.1999.819886
