Title :
A 256Gb NAND Flash Memory Stack with 300MB/s HLNAND Interface Chip for Point-to-Point Ring Topology
Author :
Gillingham, Peter ; Kim, Jin-Ki ; Schuetz, Roland ; Pyeon, Hong-Beom ; Oh, HakJune ; MacDonald, Don ; Choi, Eric ; Chinn, David
Author_Institution :
MOSAID Technol. Inc., Kanata, ON, Canada
Abstract :
A 256Gb NAND flash device includes eight stacked 32Gb MLC die and a 16.2mm2 HLNAND interface chip providing a 300MB/s synchronous DDR point-to-point ring topology system interface. Four internal busses supporting both 40MHz asynchronous NAND or 133MHz toggle mode NAND allow independent, concurrent operation of the MLC die. The device features data truncation power savings, programmable page size, and command packet error detection.
Keywords :
NAND circuits; flash memories; HLNAND interface chip; MLC die; NAND flash memory stack; bit rate 300 Mbit/s; command packet error detection; data truncation power saving; frequency 133 MHz; frequency 400 MHz; memory size 256 GByte; programmable page size; synchronous DDR point-to-point ring topology system interface; Clocks; Flash memory; Pins; Random access memory; Registers; Throughput; Topology;
Conference_Titel :
Memory Workshop (IMW), 2011 3rd IEEE International
Conference_Location :
Monterey, CA
Print_ISBN :
978-1-4577-0225-9
Electronic_ISBN :
978-1-4577-0224-2
DOI :
10.1109/IMW.2011.5873241
