LDPC code construction with flexible hardware implementation

This paper presents an LDPC code construction technique for irregular codes of various block sizes and code rates, thus obtaining the performance benefit of irregular distributions. It represents an extension of the methods presented by Sridhara et al. [2001] for regular codes. More importantly, an efficient and practical decoder architecture is also presented that achieves flexibility in block size and code rate for this broad family of codes, a capability not present in other approaches. This decoder can also achieve a high degree of parallelism, thus exploiting one of the benefits of belief propagation.