Title :
A novel low-voltage silicon-on-insulator (SOI) CMOS complementary pass-transistor logic (CPL) circuit using asymmetrical dynamic threshold pass-transistor (ADTPT) technique
Author :
Wang, Bo-Ting ; Kuo, James B.
Author_Institution :
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
Abstract :
Reports a novel low-voltage silicon-on-insulator (SOI) CMOS complementary pass-transistor logic (CPL) circuit using asymmetrical dynamic threshold pass-transistor (ADTPT) technique., Using the ADTPT technique to dynamically control the body bias of the pass-transistor via only one auxiliary transistor, the new SOI CMOS complementary pass-transistor logic (CPL) circuit provides superior speed performance at a low supply voltage as compared to the conventional pass-transistor logic circuits without the ADTPT technique as verified by the MEDICI simulation results. The ADTPT technique is especially effective for use in CPL circuits with serially-connected multiple inputs
Keywords :
CMOS logic circuits; VLSI; circuit simulation; logic simulation; silicon-on-insulator; CMOS complementary pass-transistor logic circuit; CPL circuits; MEDICI simulation results; SOI; asymmetrical dynamic threshold pass-transistor technique; body bias; serially-connected multiple inputs; speed performance; supply voltage; CMOS logic circuits; CMOS technology; Circuit simulation; Logic circuits; Low voltage; Medical simulation; Silicon on insulator technology; Threshold voltage; Very large scale integration; Voltage control;
Conference_Titel :
Circuits and Systems, 2000. Proceedings of the 43rd IEEE Midwest Symposium on
Conference_Location :
Lansing, MI
Print_ISBN :
0-7803-6475-9
DOI :
10.1109/MWSCAS.2000.952851
