Ultra thinning of wafer for embedded wafer packaging

Wafer thinning has been an important topic in the semiconductor industry. The trend in microelectronic industry is getting thinner and smaller packages. During the process of wafer thinning and sawing, die cracks and thus leading to failures. This problem becomes more significant, when the chip thickness becomes less than 50 ¿m. In this paper, wafer thinning parameters and its effect on the die strength has been reported. A design of experiment (DOE) has been designed to systematically analyze the wafer thinning processes. Established processes for ultra wafer thinning of 40 um thickness and die strength characterization results were given in this paper. The wafer sub-surface damages after grinding and stress relieving processed have been reported.