DocumentCode :
3519395
Title :
Electrical analysis of mechanical stress induced by shallow trench isolation
Author :
Jiang, Yanfeng ; Ju, Jiaxin
Author_Institution :
Microelectron. Center, North China Univ. of Technol., Beijing, China
fYear :
2009
fDate :
10-13 Aug. 2009
Firstpage :
1236
Lastpage :
1239
Abstract :
In many modern technologies, shallow trench isolation (STI) exhibits a potential application, especially for power devices or SOI ones. During its application, technologies have found the mechanical stress which originated from STI technology. This paper describes the usage of STI on power devices, which fulfills 700 V technology on 100 V BCD technology. Main results are the mobility variations with stress, the strong effect of Rsd on transistors. Then using the same approach on short devices with different distances gate edge to STI, we show how to evaluate stress distribution induced by STI as well as its mean value under the gate of the devices. These results help to understand, minimize or optimize stress effects.
Keywords :
BiCMOS integrated circuits; isolation technology; power transistors; silicon-on-insulator; BCD technology; SOI device; Si-SiO2; bipolar CMOS DMOS tecnology; electrical analysis; mechanical stress; mobility variation; power device; shallow trench isolation; transistor; voltage 100 V; voltage 700 V; CMOS technology; Dielectric substrates; Dielectrics and electrical insulation; Etching; Isolation technology; MOSFETs; Production; Silicon on insulator technology; Stress; Voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronic Packaging Technology & High Density Packaging, 2009. ICEPT-HDP '09. International Conference on
Conference_Location :
Beijing
Print_ISBN :
978-1-4244-4658-2
Electronic_ISBN :
978-1-4244-4659-9
Type :
conf
DOI :
10.1109/ICEPT.2009.5270598
Filename :
5270598
Link To Document :
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