A smart approach for process variation correlation modeling

Process variation has become a serious concern in nanometer technologies. Designs with competitive margins rely on well-characterized statistical models, which must predict the magnitude and scalability of variability accurately. In this paper, we propose a novel approach in creating the statistical models, which tracks the global variation correlation among logic and SRAM devices, hence more realistic. The simulation result is verified with TSMC N28 technology silicon. Two types of circuits, SRAM Vccmin calibration and a SRAM tracking circuit with logic, are discussed in this paper. Different simulation setups are applied on these two circuits to understand the impact of device correlation for the SRAM performance and design margin setting.