Title :
A parameterized SPICE macromodel of resistive random access memory and circuit demonstration
Author :
Chang, Huan-Lin ; Li, Hsuan-Chih ; Liu, C.W. ; Chen, F. ; Tsai, M.-J.
Author_Institution :
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
Abstract :
A parameterized SPICE macromodel of resistive random access memory (RRAM) is demonstrated to simulate the memory chip. The two-terminal RRAM model has the features of (1) initial condition settings of high resistance state (HRS) or low resistance state (LRS) (2) a forming behavior option (3) DC/transient mode selection (4) unipolar/bipolar mode selection, and (5) multilevel cell (MLC) operation. The features have been verified in the simulation of memory peripheral circuits with good convergence.
Keywords :
SPICE; integrated circuit modelling; random-access storage; DC-transient mode selection; RRAM; circuit demonstration; memory chip; memory peripheral circuit simulation; multilevel cell operation; parameterized SPICE macromodel; resistive random access memory; two-terminal RRAM model; unipolar-bipolar mode selection; Computer architecture; Integrated circuit modeling; Mathematical model; Microprocessors; Resistance; SPICE; Switches;
Conference_Titel :
Simulation of Semiconductor Processes and Devices (SISPAD), 2011 International Conference on
Conference_Location :
Osaka
Print_ISBN :
978-1-61284-419-0
DOI :
10.1109/SISPAD.2011.6034967
