Thermal stress analysis and structural optimization of ultra-thin chip stacked package device

Electronic package devices often endure a substantial number of thermal loading during working. Due to the mismatch of the materials´ CTE, the thermal stress can accumulate in the device´s interior, which would cause device failure such as die crack, warpage and so on. Especially for the popular multi-chip stacked package, single-chip requires thinner, the tensile strength of chip becomes very small correspondingly. Under the thermal stress the reliability of ultra-thin chip appears more important. At present, little is seen on the study of ultra-thin chip stacked package´s reliability at home. In this paper, a 2D parametric finite element model of six ultra-thin die stacked package by QFN is built through element analysis software. Thermal stress distribution and warpage deformation of the device after reflow loading were analyzed. Based on this, by adopting uniform design method and regression analysis, select part of sensitivity structural parameters to optimize the device. The purpose is minimizing thermal stress of the ultra-thin die. The results show that the maximum stress appears at the bottom passive chip; the structure of the largest warpage is at the upper corner of the EMC. From center to out of the package, the deformation appears more and more serious; the thickness of copper pad, die and EMC is the key factors. Thermal stress can be effectively lowered down by choosing optimal structural parameters. The results provide a theoretical basis for the structural size design and could improve the reliability of the package.