DocumentCode :
3519771
Title :
Stacked wire interconnect technology — Cu wire on Au bump bonding methodology
Author :
San, L.S. ; Krishna, Venkata ; Fei, C.C.
Author_Institution :
Infineon Technol. Malaysia, Batu Berendam, Malaysia
fYear :
2009
fDate :
9-11 Dec. 2009
Firstpage :
741
Lastpage :
745
Abstract :
Historically in the semiconductor industry, majority of interconnect materials used for wire bonding are Au and Al wires which are matured technologies. In regards of today´s range of advance packages, thin metallization (<0.8¿m) remains a challenges for back end assembly, especially on power semiconductor with thicker wire interconnects. In quest of this requirement, a new interconnect method have been developed by placing Au bump first on thin Al bond pad metallization follow by conventional Cu wire bonding, which effectively enables 50¿m Cu wire bonding on thin metallization without changes on existing front end technologies. It also prevents changing on current chips design and helps on overall product cost saving. Furthermore, this new convention of bonding also helps with packages with large down-sets between leads and die-pads. While Au-Al interface IMC behavior has been well established over the years, substantial investigations have been done into the Cu-Al interface IMC in the recent years. However, with this new interconnect method, a new Cu-Au-Al interface was introduced, hence this Cu-Au-Al interface integrity is yet to be assessed and study. In this paper the characteristic and the behavior of Cu-Au-Al interface have been study where the samples have subjected to high temperature storage life @150°C up to 2000hrs. Assessment results reveal a good integrity of Cu-Au interface, with no obvious formations of kirkendall voids or cracks. The IMC layer was found to have slow growth rates compared to the Au-Al system. High temperature storage and humidity stress tests have shown good bond integrity and reliability, with minimal drop in the pull & shear results.
Keywords :
aluminium alloys; copper alloys; gold alloys; integrated circuit interconnections; integrated circuit metallisation; integrated circuit reliability; lead bonding; CuAuAl; aluminum wires; back end assembly; copper wire; cracks; gold bump bonding; kirkendall voids; power semiconductor; reliability; semiconductor industry; stacked wire interconnect technology; temperature 150 degC; thin metallization; wire bonding; Assembly; Bonding; Chip scale packaging; Electronics industry; Gold; Metallization; Semiconductor device packaging; Semiconductor materials; Temperature; Wire;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronics Packaging Technology Conference, 2009. EPTC '09. 11th
Conference_Location :
Singapore
Print_ISBN :
978-1-4244-5099-2
Electronic_ISBN :
978-1-4244-5100-5
Type :
conf
DOI :
10.1109/EPTC.2009.5416453
Filename :
5416453
Link To Document :
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