A high clock-offset tolerance for DSSS synchronization

Author

Liu, Hsuan-Yu ; Tzeng, Shuenn-Der ; Liu, Yi-Chuan ; Wang, Chung-Cheng ; Hsu, Terng-Ren ; Hsu, Terng-Yin ; Lee, Chen-Yi

Author_Institution

Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan

Volume

2

fYear

2000

fDate

2000

Firstpage

944

Abstract

A dynamic ADC sampling methodology based on error-tracking loop is proposed in this paper to improve synchronized performance in DSSS baseband transceivers. To maintain the synchronized performance the ADC sampling rate is controlled by error-tracking loop to let clock offset become lower. For 1.8 MHz clock offset based on 44 MHz ADC sampling rate the BER of DSSS baseband transceivers can achieve 10^-5 in AWGN channel

Keywords

AWGN channels; analogue-digital conversion; error statistics; land mobile radio; spread spectrum communication; synchronisation; transceivers; 1.8 MHz; 44 MHz; AWGN channel; BER; DSSS synchronization; baseband transceivers; clock-offset tolerance; direct-sequence spread spectrum transceivers; dynamic ADC sampling; error-tracking loop; synchronized performance; Autocorrelation; Baseband; Bit error rate; Clocks; Error correction; Frequency synchronization; Local oscillators; Sampling methods; Spread spectrum communication; Transceivers;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2000. Proceedings of the 43rd IEEE Midwest Symposium on

Conference_Location

Lansing, MI

Print_ISBN

0-7803-6475-9

Type

conf

DOI

10.1109/MWSCAS.2000.952909

Filename

952909