DocumentCode :
3520211
Title :
Reconfigurable MPSoC versus GPU: Performance, power and energy evaluation
Author :
Göhringer, Diana ; Birk, Matthias ; Dasse-Tiyo, Yves ; Ruiter, Nicole ; Hübner, Michael ; Becker, Jürgen
Author_Institution :
Fraunhofer IOSB, Ettlingen, Germany
fYear :
2011
fDate :
26-29 July 2011
Firstpage :
848
Lastpage :
853
Abstract :
Different characteristics of algorithms, perform better or worse on various target hardware. The consequent of this is, that the selection of one suitable hardware, such as Graphic Processing Units (GPU), Field Programmable Gate Arrays (FPGAs) or traditional processor cores is a challenging task for developers. The challenge is to choose the most suitable platform satisfying the requirements of the given application, such as real-time and power- / energy consumption constraints. Due to short time to market pressure, a fast development cycle is also a very important characteristic in industrial applications. This work evaluates the performance, power- /energy consumption and the development effort for three processor-based systems: an FPGA-based multiprocessor platform called RAMPSoC, a GPU and a CPU. Two real-world applications have been selected for this evaluation: 3D Ultrasound Computer Tomography and Object Recognition. The paper presents the realization of the applications on the different target hardware and discusses the results of the power and performance evaluation.
Keywords :
computer graphic equipment; computerised tomography; coprocessors; field programmable gate arrays; multiprocessing systems; object recognition; performance evaluation; reconfigurable architectures; system-on-chip; ultrasonic imaging; 3D ultrasound computer tomography; CPU; FPGA-based multiprocessor platform; GPU; RAMPSoC; development cycle; energy consumption constraint; field programmable gate array; graphic processing units; object recognition; power consumption constraint; processor core; processor-based system; real-time constraint; reconfigurable MPSoC; Field programmable gate arrays; Finite impulse response filter; Graphics processing unit; Hardware; Instruction sets; Kernel; Object recognition;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Industrial Informatics (INDIN), 2011 9th IEEE International Conference on
Conference_Location :
Caparica, Lisbon
Print_ISBN :
978-1-4577-0435-2
Electronic_ISBN :
978-1-4577-0433-8
Type :
conf
DOI :
10.1109/INDIN.2011.6035003
Filename :
6035003
Link To Document :
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