DocumentCode :
3520367
Title :
Experimental methods in monitoring voids formation during flip chip underfill cure process
Author :
Seng, Foong Chee ; Xian, Tee Swee ; Ling, Wong Tzu
Author_Institution :
Freescale Semicond. (M) Sdn. Bhd., Petaling Jaya, Malaysia
fYear :
2009
fDate :
9-11 Dec. 2009
Firstpage :
556
Lastpage :
561
Abstract :
In this paper, we discuss a unique combination of experimental analyses employed to monitor, understand, and ultimately eliminate micro voids formation in the epoxy matrix of flip chip underfill during curing. Present day flip chip packages require the use of underfill epoxies to achieve reliable C4 bumps solder joints on the board level. Many different types of underfill epoxy chemistry have been used to varying degree of success. In the case of a particular Freescale high end communication processor packaged in ceramics flip chip, Moisture Resistant Cyanate Ester (MRCE) underfill was determined to offer the optimal board level reliability. Unfortunately, MRCE based underfill is also prone to micro voids formation during curing process. Micro voids trapped in the underfill matrix deteriorate the overall package and board level reliability. In order to eliminate these micro voids, it is important to understand the void formation mechanisms. Reliable methods are required to detect not only the presence of these micro voids, but also the on-set of the micro voids during cure. In typical experiments, only fully cured samples are examined for voids. In the work presented here, we describe a series of experimental analyses that helped us to detect the on-set of the micro voids formation during curing. With knowledge of the micro voids formation on-set at different stages of the cure, we were able to modify the cure parameters to eliminate these voids. Specifically, we have made use of standard video cameras and mechanical cross sectioning to capture evidence of voids formation at different stages of the cure. Differential Scanning Calorimetry (DSC) was used extensively to study the thermal properties of both epoxy underfill and to simulate the heating processes that these materials undergo at assembly. Thermal Gravimetric Analysis (TGA) was used to confirm the micro voids formation mechanism. Scanning Acoustic Microscopy (SAM) was used to confirm the voids formed and voi- ds distribution in the FC-CBGA package in actual assembly process. To complete the analyses, the visual observations were correlated to the measured physical changes and chemical kinetics of the MRCE epoxy. Putting all these information together, we were able to come up with a robust solution to eliminate the micro voids effectively.
Keywords :
ceramics; circuit reliability; curing; differential scanning calorimetry; flip-chip devices; solders; FC-CBGA package; MRCE epoxy; MRCE underfill; actual assembly process; ceramics flip chip; chemical kinetics; cure parameters; curing process; differential scanning calorimetry; epoxy matrix; epoxy underfill; flip chip packages; flip chip underfill cure process; freescale high end communication processor; heating process; mechanical cross sectioning; microvoids formation; moisture resistant cyanate ester; optimal board level reliability; package reliability; reliable C4 bumps solder joints; scanning acoustic microscopy; standard video cameras; thermal gravimetric analysis; thermal properties; underfill epoxies; underfill epoxy chemistry; underfill matrix; void formation mechanisms; voids distribution; Assembly; Ceramics; Chemical analysis; Chemistry; Curing; Flip chip; Moisture; Monitoring; Packaging; Soldering; Flip Chip CBGA; MRCE; micro void; underfill;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronics Packaging Technology Conference, 2009. EPTC '09. 11th
Conference_Location :
Singapore
Print_ISBN :
978-1-4244-5099-2
Electronic_ISBN :
978-1-4244-5100-5
Type :
conf
DOI :
10.1109/EPTC.2009.5416487
Filename :
5416487
Link To Document :
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