Design of silicon on insulator (SOI) SiGe p-MOSFET for CMOS applications

A lot of research has been done in the area of silicon on insulator and silicon-germanium technologies. There is also a great deal of interest in combining those two technologies. The major benefit is to improve the performance of pMOSFET which is limited by lower hole mobility. In this paper we present a systematic study of scaling properties of SOI Si and SiGe p-MOSFETs by using two-dimensional numerical simulation. It was found that for both Si and SiGe devices, n ⁺ gate is well suited for the design of fully depleted devices. This design requires p⁺ doping spike for threshold voltage adjustment. Using n⁺ gate we can design a device that is very lowly doped, fully depleted, satisfies all the design criteria, has small threshold voltage (V_TH) sensitivity to the silicon film thickness (t_Si) and has sharp subthreshold slope. The SiGe device shows increase in linear transconductance of 24%, smaller increase in saturation transconductance, improved current drive and extended range of design options compared to Si device. Our results also indicate that reduction of the silicon film thickness is more effective way of controlling short channel effects in low doped n⁺ gate designs than increase in doping. It is possible to design fully depleted n⁺ gate device with short channel lengths which has low threshold voltage dependence on silicon film thickness. This is done by utilizing the silicon film thickness dependence of: (1) the total charge under the gate, and (2) source-body potential barrier. If the thickness is reduced, the first effect reduces while the second one increases the threshold voltage making the dependence of the threshold voltage on silicon film thickness acceptable