• DocumentCode
    3520688
  • Title

    Alignment and overlay characterization for 3D integration and advanced packaging

  • Author

    Zeijl, H. W v ; Sarro, P.M.

  • Author_Institution
    Lab. of Electron. Mater. Devices & Components (ECTM), Delft Univ. of Technol., Delft, Netherlands
  • fYear
    2009
  • fDate
    9-11 Dec. 2009
  • Firstpage
    447
  • Lastpage
    451
  • Abstract
    The alignment and overlay performance of an ASML PAS5000 waferstepper is reviewed in relation to 3D integration and wafer level packaging (WLP) processes. The alignment system can be used to measure substrate distortions in wafer bonding and waferthinning processes and it can align with high accuracy through thick films. Moreover, it is demonstrated that in through silicon vias (TSV) processing the front- to backwafer overlay accuracy is limited by the etch process, not by the alignment system. An accurate fully functional alignment system can therefore be used to characterize and improve the overlay in 3D integration and WLP processes.
  • Keywords
    semiconductor technology; three-dimensional integrated circuits; wafer level packaging; 3D integration; ASML PAS5000 waferstepper; advanced packaging; alignment system; overlay characterization; substrate distortion; through silicon vias processing; wafer level packaging; waferthinning processes; CMOS technology; Distortion measurement; Electric variables measurement; Fabrication; Lithography; Optical distortion; Optical films; Packaging; Production; Wafer scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electronics Packaging Technology Conference, 2009. EPTC '09. 11th
  • Conference_Location
    Singapore
  • Print_ISBN
    978-1-4244-5099-2
  • Electronic_ISBN
    978-1-4244-5100-5
  • Type

    conf

  • DOI
    10.1109/EPTC.2009.5416504
  • Filename
    5416504