Title :
An architecture for a verilog hardware accelerator
Abstract :
An architecture of a verilog hardware accelerator is presented. In addition to logic simulation using discrete event simulation in hardware, other aspects of the verilog language, including behavioral simulation, module path delays, and timing checks are addressed in the context of a hardware accelerator
Keywords :
circuit analysis computing; computer architecture; delays; discrete event simulation; hardware description languages; logic CAD; pipeline processing; reduced instruction set computing; timing; virtual machines; behavioral simulation; discrete event simulation; logic simulation; module path delays; timing checks; verilog hardware accelerator architecture; verilog language; Acceleration; Circuit simulation; Computer architecture; Context modeling; Delay effects; Discrete event simulation; Hardware design languages; Pipelines; Timing; Wheels;
Conference_Titel :
Verilog HDL Conference, 1996. Proceedings., 1996 IEEE International
Conference_Location :
Santa Clara, CA
Print_ISBN :
0-8186-7431-8
DOI :
10.1109/IVC.1996.496011
