DocumentCode
3520785
Title
Critical analysis of 14nm device options
Author
Oldiges, P. ; Muralidhar, R. ; Kulkarni, P. ; Lin, C-H ; Xiu, K. ; Guo, D. ; Bajaj, M. ; Sathaye, N.
Author_Institution
Syst. & Technol. Group, IBM Corp., Hopewell Junction, NY, USA
fYear
2011
fDate
8-10 Sept. 2011
Firstpage
5
Lastpage
8
Abstract
Modeling challenges and solutions for silicon based high performance device options at the 14nm node are presented. A variety of devices are being considered, using a variety of methods to analyze the devices objectively. Partially depleted silicon on insulator (PDSOI) devices are compared against extremely thin (ETSOI) and FinFET devices.
Keywords
MOSFET; elemental semiconductors; silicon; silicon-on-insulator; ETSOI device; FinFET device; PDSOI device; Si; critical analysis; extremely thin silicon on insulator device; partially depleted silicon on insulator device; size 14 nm; Equations; FinFETs; Logic gates; Mathematical model; Performance evaluation; Semiconductor device modeling; Semiconductor process modeling; 14nm technology; ETSOI; FinFET; PDSOI; TCAD; performance modeling;
fLanguage
English
Publisher
ieee
Conference_Titel
Simulation of Semiconductor Processes and Devices (SISPAD), 2011 International Conference on
Conference_Location
Osaka
ISSN
1946-1569
Print_ISBN
978-1-61284-419-0
Type
conf
DOI
10.1109/SISPAD.2011.6035034
Filename
6035034
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