Reliability consequences of the chip-package interactions

In general an IC needs to be assembled before being put on a microelectronics board by the end customer. The materials of which the IC is made and the materials for the assembly normally have different thermo-mechanical behavior. Temperature changes during manufacturing, testing and application will therefore cause stresses in the materials. These stresses, in extreme cases, may cause serious damages to the ICs, especially at the corners of the chip. Besides efforts of process improvements and material optimization for both packaging and IC manufacturing, proper measures need to be taken in IC design in order to eliminate/suppress the problem sufficiently. Towards this end, Virtual Prototyping is performed to estimate the stresses within the backend stack of the chip. With the help of these simulations, the most sensitive locations within the structure are identified; these may lead to design rules. This paper described two industrial case studies in which chip-package interactions are found to be crucial for the reliability of the product.