DocumentCode :
3521089
Title :
The Verilog Procedural Interface for the Verilog Hardware Description Language
Author :
Dawson, Charles ; Pattanam, Sathyam K. ; Roberts, David
Author_Institution :
Cadence Design Syst. Inc., San Jose, CA, USA
fYear :
1996
fDate :
26-28 Feb 1996
Firstpage :
17
Lastpage :
23
Abstract :
The Verilog Procedural Interface is a new C programming interface for the Verilog Hardware Description Language. Different Verilog HDL based tools such as simulators, synthesizers, timing analyzers, and parsers could support this interface for applications which extend the tool´s functionality. VPI is part of the IEEE 1364 Programming Language Interface standard. VPI is considered to be the third generation procedural interface to Verilog HDL. The first two generations evolved in conjunction with Verilog-XL and the Verilog HDL. This process resulted in interfaces which lacked consistency and functionality for applications. VPI provides a consistent object-oriented access to the complete Verilog HDL language as described in the IEEE 2364 Language Reference Manual. VPI also provides a well defined interface for supporting Verilog-HDL based simulation. It is believed that this interface can be easily extended to meet future needs. A major portion of the VPI functionality is available in the Verilog-XL 2.2 simulator released in 9502. The complete VPI functionality will be available in the Verilog-XL 2.3 simulator to be released in 9504. The paper briefly discusses the evolution of the Verilog HDL programming language interfaces features of the VPI interface, and a set of possible powerful applications
Keywords :
IEEE standards; application program interfaces; circuit analysis computing; hardware description languages; logic CAD; software standards; C programming interface; IEEE 1364 Programming Language Interface standard; Verilog HDL based tools; Verilog Hardware Description Language; Verilog Procedural Interface; Verilog-HDL based simulation; Verilog-XL 2.2 simulator; Verilog-XL 2.3 simulator; consistent object-oriented access; parsers; simulators; synthesizers; third generation procedural interface; timing analyzers; Analytical models; Application software; Computer languages; Delay; Hardware design languages; Logic programming; Object oriented modeling; Software testing; Synthesizers; Timing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Verilog HDL Conference, 1996. Proceedings., 1996 IEEE International
Conference_Location :
Santa Clara, CA
ISSN :
1085-9403
Print_ISBN :
0-8186-7431-8
Type :
conf
DOI :
10.1109/IVC.1996.496013
Filename :
496013
Link To Document :
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