Title :
A repartitioning and HW/SW partitioning algorithm to the automatic design space exploration in the co-synthesis of embedded systems
Author :
Do Nascimento, Francisco Assis M ; Rosenstiel, Wolfgang
Author_Institution :
Wilhelm-Schickard-Inst. fur Inf., Tubingen Univ., Germany
Abstract :
Presents a co-synthesis algorithm that combines. repartitioning and HW/SW partitioning of the processes in a system specification to provide an efficient design space exploration strategy. The algorithm is defined on a partial order based Model (POM)., which is an alternative to model concurrency at a high level of abstraction and has a concise symbolic representation, mainly for systems with a high degree of parallelism, as well as allowing the use of efficient reachability analysis techniques based on partial order reductions. Our repartitioning algorithm generates a partitioning tree. where the possible partitions of the processes in a specification are represented in a systematic way, according to the communication among them. The HW/SW partitioning algorithm is applied on these possible partitionings and will select the one that minimizes the communication cost between the partitions. In this paper. we present the repartitioning, HW/SW partitioning and performance/cost estimates algorithms and how they are used in the design space exploration strategy. The reported experimental results show the efficiency., when compared with related works, and practicability of our co-synthesis algorithms
Keywords :
embedded systems; hardware-software codesign; logic partitioning; reachability analysis; symbol manipulation; trees (mathematics); HW/SW partitioning algorithm; automatic design space exploration; co-synthesis; communication cost; embedded systems; partial order based model; partitioning tree; performance/cost estimates; reachability analysis techniques; repartitioning algorithm; symbolic representation; system specification; Algorithm design and analysis; Boolean functions; Concurrent computing; Control systems; Costs; Data structures; Partitioning algorithms; Performance analysis; Process design; Space exploration;
Conference_Titel :
Integrated Circuits and Systems Design, 2001, 14th Symposium on.
Conference_Location :
Pirenopolis
Print_ISBN :
0-7695-1333-6
DOI :
10.1109/SBCCI.2001.953008