Polysilicon interconnections (FEOL): Fabrication and characterization

Three dimensional silicon integration technologies are gaining considerable attention as the traditional CMOS scaling becoming more challenging and less beneficial. The advanced packaging solutions based on thin silicon carrier are being developed to interconnect integrated circuits and other devices at high densities. A key enabling technology element of the silicon carrier is through silicon via (TSV), which can provide vertical interconnects in stacked ICs. In this paper, we present vias-first process to realize vertical interconnects that is fully FEOL compatible. The vias are filled by doped polysilicon and wafers with such pre-fabricated vias can be used as the starting wafers for any CMOS device processing. The process details and their characterization are elaborated along with the physical and electrical analysis of such vias.