A fast asynchronous re-configurable architecture for multimedia applications

Author

Rettberg, Achim ; Kleinjohann, Bernd

Author_Institution

C-LAB, Paderborn Univ., Germany

fYear

2001

fDate

2001

Firstpage

150

Lastpage

155

Abstract

In this paper we describe a fast re-configurable asynchronous architecture for multimedia applications. The asynchronous architecture reflects the data-flow characteristics of such multimedia applications. As an example we realized the DCT/IDCT algorithms. These algorithms are used for MPEG encoding and decoding. The realized DCT/IDCT algorithms are based on those of Chen-Wang (1984). It is known as one of the most efficient implementations of the DCT/IDCT algorithms. Each DCT/IDCT consists of multiplications and additions. We realized one operator network of different asynchronous components to map the DCT and the IDCT on it. Furthermore, first simulation results of VHDL models show, the effectiveness of the approach

Keywords

asynchronous circuits; discrete cosine transforms; hardware description languages; multimedia systems; reconfigurable architectures; video coding; DCT/IDCT algorithm; MPEG decoding; MPEG encoding; VHDL simulation; addition; asynchronous reconfigurable architecture; data flow; multimedia applications; multiplication; operator network; Clocks; Computer architecture; Delay; Design methodology; Discrete cosine transforms; Logic design; Protocols; Signal design; Signal processing algorithms; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Integrated Circuits and Systems Design, 2001, 14th Symposium on.

Conference_Location

Pirenopolis

Print_ISBN

0-7695-1333-6

Type

conf

DOI

10.1109/SBCCI.2001.953019

Filename

953019