• DocumentCode
    3521417
  • Title

    Extending sequencing graphs for reconfigurable applications modeling

  • Author

    Adario, A.M.S. ; Bampi, Sergio

  • Author_Institution
    Campus Erechim, URI, Erechim, Brazil
  • fYear
    2001
  • fDate
    2001
  • Firstpage
    161
  • Lastpage
    166
  • Abstract
    This paper introduces an extension to the sequencing graphs used in traditional high-level synthesis. The reconfigurable sequencing graph is a supergraph that includes reconfiguration steps indicating when and what must be changed in a configuration. In addition, the RSG allows defining the kind of reconfiguration necessary to implement an application. With the RSG, it is also possible to determine in which programmability classes the architecture is classified. Modeling with RSG is independent of technology, because it works in high-level of abstraction, but it can include physical characteristics, in order to better determine the transformations in the reconfiguration graph
  • Keywords
    graphs; high level synthesis; reconfigurable architectures; RSG; high-level synthesis; modeling; programmability; reconfigurable sequencing graph; sequencing graphs; static design; supergraph; transformations; Circuits; Field programmable gate arrays; Flow graphs; Hardware; High level synthesis; Informatics; Microprocessors; Partitioning algorithms; Prototypes; Reconfigurable architectures;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Integrated Circuits and Systems Design, 2001, 14th Symposium on.
  • Conference_Location
    Pirenopolis
  • Print_ISBN
    0-7695-1333-6
  • Type

    conf

  • DOI
    10.1109/SBCCI.2001.953021
  • Filename
    953021