Power optimized Viterbi decoder implementation through architectural transforms

Viterbi is an algorithm for error correction in the transmission of messages. It requires coding and decoding stages in the sender and receiver, respectively. These type of algorithms are very useful for the transmission of a type of message where some degree of error in the received message is acceptable, such as, voice and video. The coding allows some error detection and correction. In this paper we present an architecture for the Viterbi decoder Using this initial structure, we have applied a set of transformation techniques aiming for a power optimized implementation. These techniques include pipelining, operation reduction/substitution and the reduction of transition activity. We show that it is possible to reduce the circuit´s power consumption by more than half without impacting excessively on the area