Synthesis of multi-burst controllers as modified Huffman machines

Asynchronous design methodologies for I/O circuits start from a Signal Transition Graph (STG) specification implementing circuits based on sum-of-products+latch. The limitations of such an approach are: the STG specification does not allow the use of level sensitive signals to describe choices and the necessity to use complex cells (non-standard libraries). Furthermore, the synthesis methodologies are limited to simple circuits, because the (intermediate) state graph representation grows exponentially with the number of input signals. In this paper we describe a design methodology that starts from a multi-burst graph, MBG, specification and generates modified Huffman machines (only sum-of-products). The MBG describes the behavior as a sequence of bursts and multi-bursts. The latter are described using three burst operators: OR, XOR and concurrence. These operators are used to describe a (limited) amount of I/O concurrency. Level sensitive signals are allowed. State transitions have an intermediate representation which grows linearly with the number of signals, hence not limiting the synthesis methodology to small circuits. A theoretical background has been developed to guarantee critical race and hazard free operation. The resulting MHM are simpler (only sum-of products) and present a better latency than alternative I/O asynchronous circuits