Title :
On the use of Verilog HDL in the conversion of existing hardware designs to newer technology
Author_Institution :
Comput Group, Motorola Inc., USA
Abstract :
The trend towards greater integration of hardware continues, with the attendant benefits of increased density, speed, manufacturability, and reliability. When the updating of an existing design to a new hardware technology becomes necessary, its adaptation must allow for the differences in speed, structure and function of the new hardware medium. With the appearance of hardware description languages and the powerful CAE tools now available, the prospect of automating such a process appears plausible. We consider the “re-spin” of a board design from a TTL/PLD implementation to a gate array implementation, and the question of the automated conversion of hardware designs
Keywords :
hardware description languages; logic CAD; programmable logic arrays; system buses; CAE tools; TTL/PLD implementation; Verilog HDL; automated hardware design conversion; board design respin; design update; gate array implementation; CMOS logic circuits; CMOS technology; Clocks; Computer aided engineering; Hardware design languages; Logic arrays; Logic devices; Programmable logic arrays; Programmable logic devices; Registers;
Conference_Titel :
Verilog HDL Conference, 1996. Proceedings., 1996 IEEE International
Conference_Location :
Santa Clara, CA
Print_ISBN :
0-8186-7431-8
DOI :
10.1109/IVC.1996.496016
