• DocumentCode
    3521672
  • Title

    Challenges for extra large embedded wafer level ball grid array development

  • Author

    Jing-en Luan ; Yonggang Jin ; Kim-Yong Goh ; Yiyi Ma ; Guojun Hu ; Yaohuang Huang ; Baraton, X.

  • Author_Institution
    Corp. Packaging, Eng. & Autom., STMicroelectronics, Singapore, Singapore
  • fYear
    2009
  • fDate
    9-11 Dec. 2009
  • Firstpage
    202
  • Lastpage
    207
  • Abstract
    Fan-out embedded wafer level ball grid array (eWLB) is a very promising packaging technology with many advantages in comparison to standard ball grid array packages and leadframe based packages because of smaller size, better electrical and thermal performance, higher package interconnect density and system integration possibilities at low packaging cost. It was successfully developed for medium and large-size package. However, there is strong need to develop extra large eWLB for system integration. Compared with large eWLB, there are many challenges for extra large eWLB development. Wafer or panel level warpage, package level reliability, and board level reliability are ones of the most challenging issues. In this paper, finite element modeling was used to create design rules and optimize test vehicles based on the correlation done for medium, large-size eWLB. Two test vehicles were identified for process development and reliability test. Recent progress in the extra large eWLB development is introduced in this paper, the results show that the design rule and process capability are reliable and ready for extra large molded embedded wafer level package for system integration needs.
  • Keywords
    ball grid arrays; finite element analysis; integrated circuit interconnections; integrated circuit reliability; wafer level packaging; board level reliability; electrical performance; embedded wafer level ball grid array; finite element model; higher package interconnect density; leadframe based packages; package level reliability; packaging technology; panel level warpage; thermal performance; Bridges; Costs; Dielectric thin films; Electronics packaging; Process design; Semiconductor device modeling; Space technology; Testing; Vehicles; Wafer scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electronics Packaging Technology Conference, 2009. EPTC '09. 11th
  • Conference_Location
    Singapore
  • Print_ISBN
    978-1-4244-5099-2
  • Electronic_ISBN
    978-1-4244-5100-5
  • Type

    conf

  • DOI
    10.1109/EPTC.2009.5416551
  • Filename
    5416551