Modeling and simulation of SSN on FPGA products

Simultaneous switching noise (SSN) and its behavior have recently become more and more critical in IC and other highspeed system designs [1][2]. This is attributed to ever-increasing speed, frequency, density, and power, as well as decreasing circuit dimensions and logic levels. The difference in a few mill volts may cause the system to fail. Therefore, it is very important to understand the characteristics of the SSN glitch of an active device for correct system level performance. In this paper, some methods to provide a complete picture of limitation characteristic behavior and its relationship to cause scheme, due to SSN, is demonstrated with FPGA system. Furthermore, model simulation confirms our postulations made on examination of experimental data and validates the methodology practical to SSN assessment in FPGA applications.