Design of an inter-plane circuit for clocked PLAs

Author

Wang, Chua-Chin ; Chien, Yu-Tsun ; Chen, Ying-Pei

Author_Institution

Dept. of Electr. Eng., Nat. Sun Yat-Sen Univ., Kaohsiung, Taiwan

Volume

4

fYear

2000

fDate

2000

Firstpage

281

Abstract

The Programmable Logic Arrays (PLAs) have become popular devices in realization of both combinational and sequential circuits. We present a power-saving fast half-swing CMOS circuit implementation for NOR-NOR PLA implementation. An additional 1/2 VDD voltage source and buffering transmission gates are inserted between the NOR planes to erase the racing problem and shorten the rise delay as well as the fall delay of the output response such that the speed is enhanced and the dynamic power is reduced

Keywords

CMOS logic circuits; integrated circuit design; logic design; programmable logic arrays; NOR-NOR PLA implementation; additional 1/2 VDD voltage source; buffering transmission gates; clocked PLAs; dynamic power reduction; fast half-swing CMOS circuit; inter-plane circuit design; power-saving CMOS circuit implementation; programmable logic arrays; racing problem; speed enhancement; Clocks; Delay; MOSFETs; Programmable logic arrays; Sawing; Sequential circuits; Switches; Switching circuits; Voltage; Wire;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on

Conference_Location

Geneva

Print_ISBN

0-7803-5482-6

Type

conf

DOI

10.1109/ISCAS.2000.858743

Filename

858743