An abnormal floating gate interference and a low program performance in 2y nm NAND flash devices

We have investigated a mechanism for an abnormally large floating gate (FG) interference reported in 2y nm NAND flash device. Based on the experimental and simulation results, we have found that the root cause is attributed to a depletion of polysilicon (poly-Si) layer for the control gate (CG). It was also found that the poly-Si depletion gives deterioration in the program performance. This work suggests that the poly-Si depletion of the CG should be controlled and considered utilizing a full 3-dimensional (3D) TCAD process and device simulations to improve the FG interference and the performance of NAND flash device beyond 2y nm technology.