• DocumentCode
    3521907
  • Title

    An optimization system with parallel processing for reducing electromagnetic interference on electronic control unit

  • Author

    Okazaki, Yuji ; Uno, Takanori ; Asai, Hideki

  • Author_Institution
    Shizuoka Univ., Hamamatsu, Japan
  • fYear
    2009
  • fDate
    9-11 Dec. 2009
  • Firstpage
    113
  • Lastpage
    118
  • Abstract
    In this paper, we propose an optimization system with parallel processing for reducing electromagnetic interference (EMI) on electronic control unit (ECU). We adopt simulated annealing (SA), genetic algorithm (GA) and taboo search (TS) to seek optimal solutions, and a SPICE-like circuit simulator to analyze common-mode current. Therefore, the proposed system can determine the adequate combinations of the parasitic inductance and capacitance values on printed circuit board (PCB) efficiently and practically, to reduce EMI caused by the common-mode current. Finally, we apply the proposed system to an example circuit to verify the validity and efficiency of the system.
  • Keywords
    SPICE; electromagnetic interference; genetic algorithms; printed circuits; simulated annealing; PCB; SPICE-like circuit simulator; common-mode current; electromagnetic interference; electronic control unit; genetic algorithm; optimization system; parallel processing; parasitic capacitance values; parasitic inductance values; printed circuit board; simulated annealing; taboo search; Algorithm design and analysis; Analytical models; Circuit analysis; Circuit simulation; Control systems; Electromagnetic interference; Genetic algorithms; Inductance; Parallel processing; Simulated annealing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electronics Packaging Technology Conference, 2009. EPTC '09. 11th
  • Conference_Location
    Singapore
  • Print_ISBN
    978-1-4244-5099-2
  • Electronic_ISBN
    978-1-4244-5100-5
  • Type

    conf

  • DOI
    10.1109/EPTC.2009.5416565
  • Filename
    5416565