Towards a formal model of hardware synthesized from Verilog

Formal verification offers a way to prevent costly design errors that are impractical to detect with simulation alone. Successful formal verification of hardware requires using automated theorem provers. Optimal synthesis requires providing high level (behavioral) Verilog to commercial synthesis tools, such as PLDesigner and Synopsys. The paper presents a novel approach, known as the volley technique, that allows a design to be coded in an analogous way both in Verilog HDL and in the LISP like syntax of the Boyer Moore theorem (R.S. Boyer and J.S. Moore, 1988). To illustrate the technique, a simple machine that computes Fibbonaci numbers is designed in Verilog and fabricated as an AMD MACH 210 CPLD