Title :
Efficient module 2n+1 multiplication schemes for IDEA
Author :
Bahrami, Masoud ; Sadeghiyan, Babak
Author_Institution :
Dept. of Comput. Eng., Amirkabir Univ. of Technol., Tehran, Iran
Abstract :
In this paper we investigate different methods of designing a module 2n+1 multiplier in binary and diminished-1 systems for International Data Encryption Algorithm (IDEATM) block cipher and propose an efficient modulo 2n+1 multiplier. To design the different stages of the binary multiplier different methods are studied and compared. A new (5:3) counter for the reduction of Wallace tree delay is proposed and a modified diminished-1 algorithm is also proposed. The superiority of diminished-1 system rather than binary system for 2n+1 module multiplication is shown. We compare our results with previous works in terms of time and area
Keywords :
cryptography; digital arithmetic; digital signal processing chips; integrated logic circuits; multiplying circuits; DSP; IDEA block cipher; International Data Encryption Algorithm; Wallace tree delay reduction; binary multiplier; binary systems; counter; diminished-1 system; module multiplication schemes; Added delay; Adders; Counting circuits; Design methodology; Encoding;
Conference_Titel :
Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on
Conference_Location :
Geneva
Print_ISBN :
0-7803-5482-6
DOI :
10.1109/ISCAS.2000.858836
