DocumentCode
3522456
Title
COMIC++: A software SVM system for heterogeneous multicore accelerator clusters
Author
Lee, Jaejin ; Lee, Jun ; Seo, Sangmin ; Kim, Jungwon ; Kim, Seungkyun ; Sura, Zehra
Author_Institution
Sch. of Comput. Sci. & Eng., Seoul Nat. Univ., Seoul, South Korea
fYear
2010
fDate
9-14 Jan. 2010
Firstpage
1
Lastpage
12
Abstract
In this paper, we propose a software shared virtual memory (SVM) system for heterogeneous multicore accelerator clusters with explicitly managed memory hierarchies. The target cluster consists of a single manager node and many compute nodes. The manager node contains a generalpurpose processor and larger main memory, and each compute node contains a heterogeneous multicore processor and smaller main memory. These nodes are connected with an interconnection network, such as Gigabit Ethernet. The heterogeneous multicore processor in each compute node consists of a general-purpose processor element (GPE) and multiple accelerator processor elements (APEs). The GPE runs an OS and the multiple APEs are dedicated to compute-intensive workloads. The GPE is typically backed by a deep on-chip cache hierarchy and hardware cache coherence. On the other hand, the APEs have small explicitly-addressed local memory instead of caches. This APE local memory is not coherent with the main memory. Different main and local memory units in the accelerator cluster can be viewed as an explicitly managed memory hierarchy: global memory, node local memory, and APE local memory. Since coherence protocols of previous software SVM proposals cannot effectively handle such a memory hierarchy, we propose a new coherence and consistency protocol, called hierarchical centralized release consistency (HCRC). Our software SVM system is built on top of HCRC and software-managed caches. We evaluate the effectiveness and analyze the performance of our software SVM system on a 32-node heterogeneous multicore cluster (a total of 192 APEs).
Keywords
cache storage; shared memory systems; APE; GPE; general purpose processor element; hardware cache coherence; heterogeneous multicore accelerator clusters; heterogeneous multicore processor; hierarchical centralized release consistency; local memory; main memory; on-chip cache hierarchy; software SVM system; software shared virtual memory system; Ethernet networks; Hardware; Memory management; Multicore processing; Multiprocessor interconnection networks; Performance analysis; Proposals; Protocols; Software systems; Support vector machines;
fLanguage
English
Publisher
ieee
Conference_Titel
High Performance Computer Architecture (HPCA), 2010 IEEE 16th International Symposium on
Conference_Location
Bangalore
ISSN
1530-0897
Print_ISBN
978-1-4244-5658-1
Type
conf
DOI
10.1109/HPCA.2010.5416633
Filename
5416633
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