Title :
High performance and low complexity Max-Log-MAP algorithm for FPGA turbo decoder
Author :
Hsu, Mao-Wsiu ; Huang, Jhin-Fang
Author_Institution :
Dept. of Electron. Eng., Nat. Taiwan Univ. of Sci. & Technol., Taipei
Abstract :
In this paper, we focus on implementing turbo decoder compliant with 3GPP spec, we adopted sliding window method with forward state metric as an accuracy initialization value and a modified Max-Log-MAP algorithm which modify extrinsic information by a scaling factor R. Then, we can implement the whole turbo decoder with a single-decoder structure, producing high data throughput with lower logic gates usage. The FPGA design of our proposed structure (SW-modified Max-Log-MAP) results in only 0.1 dB away from the optimal structure (SW-Log-MAP) at BER=10-4. It also saves about 29% hardware cost than the optimal structure
Keywords :
computational complexity; error statistics; field programmable gate arrays; logic design; logic gates; maximum likelihood decoding; turbo codes; FPGA design; FPGA turbo decoder; Max-Log-MAP algorithm; logic gates; single-decoder structure; sliding window method; Cost function; Delay; Field programmable gate arrays; Hardware; Iterative algorithms; Iterative decoding; Logic gates; Noise generators; Throughput; Turbo codes;
Conference_Titel :
Advanced Communication Technology, 2005, ICACT 2005. The 7th International Conference on
Conference_Location :
Phoenix Park
DOI :
10.1109/ICACT.2005.246081
