DocumentCode :
3522617
Title :
ESP-NUCA: A low-cost adaptive Non-Uniform Cache Architecture
Author :
Merino, Javier ; Puente, Valentin ; Gregorio, Jose A.
Author_Institution :
Comput. Archit. Group, Univ. of Cantabria, Santander, Spain
fYear :
2010
fDate :
9-14 Jan. 2010
Firstpage :
1
Lastpage :
10
Abstract :
This paper introduces a cost effective cache architecture called Enhanced Shared-Private Non-Uniform Cache Architecture (ESP-NUCA), which is suitable for highperformance Chip MultiProcessors (CMPs). This architecture enhances system stability by combining the advantages of private and shared caches. Starting from a shared NUCA, ESP-NUCA introduces a low-cost mechanism to dynamically allocate private cache blocks closer to their owner processor. In this way, average on-chip access latency is reduced and inter-core interference minimized. ESP-NUCA synergistically integrates victims and replicas thus making it possible to take advantage of multiple-readers for shared data, and to maximize cache usage under unbalanced core utilization. This architecture leads to stable behavior within the whole system across a broad spectrum of working scenarios. ESP-NUCA not only outperforms architectures with similar implementation costs such as private and shared caches by up to 20% and 40% respectively, but even outperforms much costlier architectures such as D-NUCA [13] by up to 28%, Adaptive Selective Replication [3] by up to 19%, and Cooperative Caching [5] by up to 15%. Moreover, performance variance throughout the set of benchmarks is 37% lower than with ASR, 87% lower than with D-NUCA, and 43% lower than with Cooperative Caching.
Keywords :
cache storage; computer architecture; multiprocessing systems; average on-chip access latency; chip multiprocessors; enhanced shared-private non-uniform cache architecture; inter-core interference; private cache blocks; Automatic speech recognition; Computer architecture; Cooperative caching; Costs; Degradation; Delay; Interference; Proposals; Stability; Yarn;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
High Performance Computer Architecture (HPCA), 2010 IEEE 16th International Symposium on
Conference_Location :
Bangalore
ISSN :
1530-0897
Print_ISBN :
978-1-4244-5658-1
Type :
conf
DOI :
10.1109/HPCA.2010.5416641
Filename :
5416641
Link To Document :
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