Fabrication and characterization of a novel wafer-level chip scale package for MEMS devices

This paper reports a hermetic MEMS package structure with silicon wafer as bonded cap at wafer-level scale. CMP followed by spraying chemical smoothing process is utilized to thin the N(100) silicon cap wafer to the thickness of 150 mum after wafer-level Cu/Sn isothermal solidification bonding. Method for the thinning process and parameters for Cu/Sn isothermal solidification bonding process are researched and optimized. TMAH etching is used to open trenches penetrating through the cap wafer and then Pb₆₃Sn₃₇ bumps redistribution and reflow are utilized to achieve the final I/O interconnection. Such approaches have the most important features of simplified fabrication process compatibility with most MEMS processes and low-cost. Fine-leak tests as well as gross-leak tests have been done on the packaged samples in order to characterize the hermeticity of the bonded wafers which indicating an excellent leak rate of around 1.9times10^-9 atm cc/s. The shear strength of the packaged samples has been measured and average shear strength of 19.5 Mpa is achieved. Both results meet the demands of MIL-STD-883E.