ASIC design validation in a system context

The paper describes a methodology for ASIC design validation in a system simulation context. The methodology is based on using a single system level testbench across all levels of model abstraction and throughout the entire product development cycle. Topics covered include how to design a system simulation for ASIC validation, elements of a good validation plan, writing a Verilog system level testbench and testing at different model abstraction levels. The paper uses Verilog design examples from two different projects to illustrate validation of both single and multiple ASIC systems. The benefits of following this methodology to a project´s quality, time to market and predictability are shown